1. Field of the Invention
This invention relates to semiconductor devices, and, more particularly, to a backgated hybrid construction particularly useful in suppressing the effect of undesirable charge carriers in gated semiconductor devices.
2. Description of Related Art
Gated semiconductor devices are important components of many large scale and very large scale integrated circuits such as microprocessors and semiconductor memories. They are also becoming increasingly important in power control devices, as the semiconductor technology of handling high voltages and currents improves.
The most important of such gated semiconductor devices are MOSFETs (metal-oxide-semiconductor field effect transistors) and related devices. In a conventional MOSFET, a gate region separates a source region from a drain region, and under proper conditions a conductive path is formed through the gate region so that a current can flow from the source region to the drain region. The current flows by a conducting channel produced through the gate region, and the conductance of the channel can be modulated by varying the gate voltage. Large numbers of MOSFETs of various types may be fabricated together on a single substrate in an interconnected fashion to perform complex logic, memory and control functions in miniature devices. The size and scale of MOSFETs has been continually reduced as semiconductor technology has progressed over the years, to a size of about 1-5 micrometers, so that it is possible to place on the order of 100,000 to 1,000,000 components on a single substrate chip, and even greater numbers of devices on a single chip are predicted for the future.
MOSFETs and other gated devices are typically fabricated by placing the source, drain, and gate regions on a substrate such as an insulator, which insulates individual components from their neighbors in an integrated circuit. The thicknesses of the gate region and the conducting channel can be very small, on the order of 0.1 micrometers, and therefore the presence of even relatively small numbers of undesirable, stray charge carriers can significantly affect the operation of the spatial distribution of the gated device. That is, the stray charge carriers distort the gating voltage as applied to the conducting channel, thereby changing the operating characteristics or even causing failure of the component if a sufficiently great number of stray charge carriers is introduced.
Some stray charge carriers are inherently present in most gated semiconductor devices due to the presence of impurities and electrical interactions at the interfaces between regions of different composition. Continuing improvements in device fabrication techniques serve to reduce the effect of such inherent charge carriers.
On the other hand, excessive amounts of undesired charge carriers may be introduced into an integrated circuit either inadvertently in the operating environment such as space, intentionally by one who seeks to disrupt the operation of the integrated circuit device or intentionally during processing steps accomplished by electron beams or x-ray plasmas. There have been, and continue to be, extensive efforts to develop techniques for resisting disruption of integrated circuit devices as a result of the introduction of high concentrations of charge carriers into the devices, but such approaches have not yet met with complete success. Thus, there exists a need for nullifying the effect of internally or externally introduced stray charge carriers in such electronic circuits.
It is well-known to bias the substrate of a gated semiconductor device. However, when the substrate is a sapphire wafer on the order of 0.25 millimeters thick, very high biasing voltages such as on the order of 10 kilovolts must be applied to have a significant effect on the stray charge carriers which may be present adjacent the gate of the component fabricated on the top of the substrate. Such high voltages are impractical in many applications, and in addition a single high substrate biasing voltage cannot be varied or changed in polarity to provide different biasing voltages for single or grouped semiconductor devices. While such substrate biasing does tend to remove some of the undesirable stray charge carriers, the presently known biasing technology is not feasible for use in many circuit elements to achieve control of the excess charge carriers.
Therefore, there exists a need for a technique whereby a gated semiconductor device may be fabricated on an insulating substrate in such a way that stray charge carriers in the device may be controlled, and preferably removed. The approach should allow retention of conventional advantages of thick, structural insulating substrates and also be fully compatable with conventional semiconductor fabrication technologies, wherein device structures are built upwardly from a structural substrate. The present invention fulfills this need, and further provides related advantages.